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AR# 66560

UltraScale/UltraScale+ DDR3 and DDR4 IP - IP Generation Fails when Custom Part CSV File is Loaded for Twin Die Component

Description

Version Found: DDR3 and DDR 4 v1.1

Version Resolved: See (Xilinx Answer 69035) for DDR4 and see (Xilinx Answer 69036) for DDR3

When I try to generate a DDR4/3 configuration requiring a twin die component, errors similar to the following are generated:

[Mig 66-116] Custom Part (DDR3_CUSTOM) with parameter: CA Mirror having value: 0 is invalid

When I edit the .csv file to set CA Mirror to 1, the following error is displayed:

[Mig 66-116] Custom Part (DDR3_CUSTOM) with parameter: CA Mirror having value: 1 is invalid

Solution

CA_MIRROR is a DDR4/3 parameter that is set to "ON" for DIMMs that support address mirroring. Twin die parts do not use address mirroring. 

Therefore, the error message generated is not valid, and will be fixed in the 2016.1 release.

When targeting a twin die part in versions prior to 2016.1, either select one of the available default twin die parts, or if targeting a 64-bit data width, specify a SODIMM in the custom part .csv file with CA_MIRROR set to 0.

Revision History:

09/18/2017 - Linked to master DDR3 and DDR4 ARs

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
AR# 66560
Date 01/16/2018
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
  • Kintex UltraScale+
  • More
  • Virtex UltraScale+
  • Zynq UltraScale+ MPSoC
  • Less
IP
  • MIG UltraScale
  • DDR3 SDRAM
  • DDR4 SDRAM
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