Version Found:RLDRAM3 v1.1
Version Resolved: See (Xilinx Answer 69037)
For certain RLDRAM3 IP UltraScale configurations, the following placer error may be seen:
If this occurs and there are sufficient LUTRAMs still available to be placed, this is likely a known issue with the Vivado Placer.
To work around the Placer error, manually lock the RLDRAM3 IP logic to a PBLOCK in the same clock regions as the RLDRAM3 I/O.
This can be done by following the steps below:
02/10/2016 - Initial Release