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AR# 66617

2015.4 - Zynq UltraScale+ MPSoC - Program FPGA fails when targetting a xczu9eg-ffvb1156-1-i-es1

Description

I am targeting the xczu9eg-ffvb1156-1-i-es1 in Vivado. I have a MicroBlaze in the PL. 

However, if I run Program FPGA in SDK, I get the error below:

****** updatemem v2015.4_AR65982 (64-bit)
**** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
source C:/Xilinx/SDK/2015.4/scripts/updatemem/main.tcl -notrace
ERROR: [Bitstream 40-51] Unsupported part xczu9eg-ffvb1156-1-i-es1 in bitfile C:/cases/ZCU102_BoardBringup/lwip_zc102_revb/project_2/project_2.sdk/design_1_wrapper_hw_platform_0/design_1_wrapper.bit.
Loading bitfile C:/cases/ZCU102_BoardBringup/lwip_zc102_revb/project_2/project_2.sdk/design_1_wrapper_hw_platform_0/design_1_wrapper.bit
ERROR: [Bitstream 40-51] Unsupported part xczu9eg-ffvb1156-1-i-es1 in bitfile C:/cases/ZCU102_BoardBringup/lwip_zc102_revb/project_2/project_2.sdk/design_1_wrapper_hw_platform_0/design_1_wrapper.bit.
ERROR: [Updatemem 57-46] Bitfile C:/cases/ZCU102_BoardBringup/lwip_zc102_revb/project_2/project_2.sdk/design_1_wrapper_hw_platform_0/design_1_wrapper.bit could not be loaded.
ERROR: [Common 17-39] 'update_mem' failed due to earlier errors.

How can this be addressed?

Solution

This is a known issue in Vivado 2015.4 which is addressed in the 2016.1 release. To work around this issue in Vivado 2015.4, you can created the ELF in SDK, and use the MEMDATA flow to populate the BRAM INIT strings.

To do this, add the ELF as a source file in Vivado, and then right click on the ELF and select "Associate ELF Files..", then set it as follows:

You will then need to regenerate the bitstream (write_bitstream) to populate the BRAM INIT strings with the ELF data.

AR# 66617
Date Created 02/12/2016
Last Updated 02/15/2016
Status Active
Type General Article
Devices
  • Zynq UltraScale+ MPSoC
Tools
  • Vivado Design Suite - 2015.4.1
  • Vivado Design Suite - 2015.4