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AR# 66659

2015.4 Vivado Implementation : ERROR: [Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.


I see the following error during Implementation. What is the reason for this error and how can I fix it?

ERROR: [Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_in1_IBUF] >
clk_in1_IBUF_inst/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X1Y21
test (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X1Y24

The above error could possibly be related to other connected instances. Following is a list of all the related clock rules and their respective instances.


This error complains about the sub optimal placement of I/O ports and BUFG in the design. This can be seen when the clock port is locked to a non-GCIO pin or when the I/O port and BUFG instance are placed in different clock regions.

If the clock port is locked to a GCIO pin and the error is still reported then follow the steps below:

1) Open the synthesized design and run the following commands:


This runs I/O and clock placement and leaves the partially placed design for investigation. "place_ports" might report an error but you can still view the partial placement.

2) Search for the instances mentioned in the error message and mark them in device view to find out in which clock region they are placed by the tool currently.

If the I/O and BUFG instances are placed in different clock regions then check if the BUFG is constrained to an improper site by user location constraints. 

Check the IS_FIXED property of the BUFG instance to find this out. If the IS_FIXED property is set it means that it is locked by user constraints. If this is the case, modify the constraints so that the I/O port and BUFG get placed in same clock region.

3) Try locking the BUFG to the same clock region as that of I/O port using the following constraint:

set_property CLOCK_REGION XxYy [get_cells <bufg_instance_name>]
  1. This might fail with a different error which could explain why the tool was not able to place the I/O and BUFG in the same clock region.
  2. If the user constraints help in successful placement then this is a tool issue, as the tool was unable to identify a correct placement. Please open a Service request and report this issue.

You can also override the error by using the CLOCK_DEDICATED_ROUTE constraint mentioned in the error message, however this is not recommended.

AR# 66659
Date Created 02/18/2016
Last Updated 05/30/2016
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
  • Vivado Design Suite - 2015.4