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  3. AR# 66666: 2015.4 FIFO Generator: CRITICAL WARNING: [Common 17-55] warnings point to FIFO generator IP XDC file

AR# 66666

2015.4 FIFO Generator: CRITICAL WARNING: [Common 17-55] warnings point to FIFO generator IP XDC file

Description

I see the following critical warnings during Implementation:

CRITICAL WARNING: [Common 17-55] 'get_property' expects at least one object. [<>/sources_1/ip/fifo_generator_0/fifo_generator_0/fifo_generator_0_clocks.xdc:59]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
CRITICAL WARNING: [Common 17-55] 'get_property' expects at least one object. <>/sources_1/ip/fifo_generator_0/fifo_generator_0/fifo_generator_0_clocks.xdc:61]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

The messages point to the constraints present in the IP XDC file shown below:

set_max_delay -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[*].wr_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $rd_clock]

set_max_delay -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[*].rd_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $wr_clock]

How can I fix this?

Solution

There warnings will be seen if you have not defined clock period constraints on the ports or logic which is driving the rd_clk and wr_clk pins of the FIFO generator IP.

To resolve this you will need to write create_clock constraints in the top level XDC file.

AR# 66666
Date 06/27/2016
Status Active
Type General Article
Devices
  • FPGA Device Families
Tools
  • Vivado Design Suite - 2015.4.1
IP
  • FIFO Generator