Description

I see the following critical warnings during Implementation:

The messages point to the constraints present in the IP XDC file shown below:

How can I fix this?

Solution

There warnings will be seen if you have not defined clock period constraints on the ports or logic which is driving the rd_clk and wr_clk pins of the FIFO generator IP.

To resolve this you will need to write create_clock constraints in the top level XDC file.