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AR# 66685

LogiCORE IP Digital Pre-Distortion (DPD) - Release Notes and Known Issues for Vivado 2014.4 and newer tool versions


This answer record contains the Release Notes and Known Issues for the LogiCORE IP Digital Pre-Distortion core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core used in Vivado 2014.4 and newer tool versions.

Digital Pre-Distortion LogiCORE IP Page:



General Information:

Supported Devices can be found in the following three locations:

Xilinx has released Digital Pre-Distortion v7.0/v7.1/v8.0/v8.1 IP as a User Repository in the Digital Pre-Distortion(DPD) Evaluation Lounge. The lounge also gives access to the IP Product Guide, Advanced Debug Interface, Resource Estimate.

Version Table

This table correlates the core version to the compatible Vivado design tools release version. For more info about the compatibility between DPD IP and Vivado tools, refer to (Xilinx Answer 66684)

Core Version Vivado Tools Version
v8.1  2017.2
v8.0 2016.3
v8.0 EA1 2016.2
v7.1(Rev.2) 2015.4
v7.1 2015.2
v7.0 2014.4

General Guidance

The table below provides answer records for general guidance when using the LogiCORE IP Digital Pre-Distortion core.

Answer Record Title
(Xilinx Answer 66684) The compatibility between Digital Pre-Distortion IP revisions, Vivado tools and DPD IP associated debug interfaces


Known and Resolved Issues

The following table provides known issues for the LogiCORE IP Digital Pre-Distortion core, starting with v7.0.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions. i

Answer Record Title Version Found Version Resolved
(Xilinx Answer 67858) LogiCORE Digital Pre-Distortion (DPD) v7.1 rev2 or rev3 - DPD example design does not simulate correctly v7.1(Rev.2 or rev3)  
(Xilinx Answer 67806) Data format for Mnemonic LEAKAGEVALUE and DAMPINGVAALUE v7.1(Rev.2) N/A
(Xilinx Answer 67805) Changing Filter Memory Depth can cause the DPD core run to abnormally v7.1(Rev.2) v7.1(Rev.3)
(Xilinx Answer 67135) The PS in Zynq can get locked with DPD operating in AMP configuration with PetaLinux in CPU0 v7.1(Rev.2) v7.1 (Rev.3)
(Xilinx Answer 66343) Digital Pre-Distortion Debug Interface GUI does not connect to board without loading bit file for dpd_v7_1_dbg_rev1 and dpd_v7_1_dbg_rev1
v7.1 N/A
(Xilinx Answer 65803) The global timer used by Digital Pre-Distortion v7.0/v7.1 software, can cause Linux (running on CPU0 in AMP configuration) which is accessing the global timer to lock up v7.0 v7.1 (Rev.1)


Revision History

Added (Xilinx Answer 67805), Added (Xilinx Answer 67806)
Added (Xilinx Answer 67135), Added Core Version v8.0 EA1
02/24/2016 Added (Xilinx Answer 66343), Added (Xilinx Answer 65803)
02/23/2016 Initial Release

Linked Answer Records

Child Answer Records

AR# 66685
Date 08/18/2017
Status Active
Type Release Notes
  • Zynq-7000
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2015.2
  • Vivado Design Suite - 2015.4
  • More
  • Vivado Design Suite - 2016.3
  • Vivado Design Suite - 2017.2
  • Less
  • Digital Pre-Distortion (DPD)
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