Version Found: v1.0
Version Resolved: See (Xilinx Answer 69037)
After the production release of the UltraScale RLDRAM3 v1.0 IP (available with Vivado 2015.3) there was an enhancement to the system reset structure.
This is included into the IP starting in the Vivado 2016.1 release and beyond.
For customers currently in production that are unable to upgrade to Vivado 2016.1, Xilinx recommends the provided patch update be installed to take advantage of the IP improvement.
This patch contains an update to the reset structure to synchronously assert and deassert the MMCM, Fabric, RIU, and MicroBlaze modules for the entire memory subsystem.
For more information, please refer to (PG150). The patch also includes C-code enhancements for completeness of BS_RESET during calibration.
To install the patch, extract the contents of "AR66688_Vivado_2015_3_preliminary_rev1.zip" to the 2015.3 install directory (for example, C:\Xilinx\Vivado\2015.3\), then open Vivado 2015.3 and generate or regenerate all of the RLDRAM3 IP.
Note: This tactical patch is only compatible with the Vivado 2015.3 and RLDRAM v1.0 IP.
04/13/2016 - Initial Release
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