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AR# 66688

UltraScale RLDRAM3 IP - patch update recommended for 2015.3

Description

Version Found: v1.0

Version Resolved: See (Xilinx Answer 58435)

Since the production release of the UltraScale RLDRAM3 v1.0 IP (available with Vivado 2015.3) there was an enhancement to the system reset structure. This is included into the IP starting in the Vivado 2016.1 release and beyond. 

For customers currently in production that are unable to upgrade to Vivado 2016.1, Xilinx recommends the provided patch update be installed to take advantage of the IP improvement.

Solution

This patch contains an update to the reset structure to synchronously assert and deassert the MMCM, Fabric, RIU, and MicroBlaze modules for the entire memory subsystem. For more information, please refer to (PG150). The patch also includes C-code enhancements for completeness of BS_RESET during calibration.

To install the patch, extract the contents of "AR66688_Vivado_2015_3_preliminary_rev1.zip" to the 2015.3 install directory (for example, C:\Xilinx\Vivado\2015.3\), then open Vivado 2015.3 and generate or regenerate all of the RLDRAM3 IP.

Note: This tactical patch is only compatible with the Vivado 2015.3 and RLDRAM v1.0 IP.

Revision History:

04/13/2016 - Initial Release

Attachments

Associated Attachments

Name File Size File Type
AR66688_Vivado_2015_3_preliminary_rev1.zip 1 MB ZIP

Linked Answer Records

Master Answer Records

AR# 66688
Date Created 02/23/2016
Last Updated 04/13/2016
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale