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AR# 66801

2015.2 Vivado Hardware Manager: Unable to program the PL of the XC7Z035 over JTAG in Vivado 2015.2.


In Vivado 2015.2, the hardware manager successfully detects the ARM Debug Access Port (DAP) and the XC7Z035.

However, when I attempt to load the bit file into the (Programmable Logic) PL of the XC7Z035, and the hardware manager begins to program the FPGA, a hang is observed at 1% until the process is killed.


This issue has been resolved in the 2015.3 release of Vivado.

AR# 66801
Date 03/23/2016
Status Active
Type General Article
  • Vivado Design Suite - 2015.2
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