I am creating a build for a PCIe Tandem configuration with Field Updates using my script. The layout and structure appear to be correct.
However, when I add some I/Os from Bank 65 to the Stage 1 CFGIOB Pblock alongside the PERST_N port, I receive the following error:
I get the same error on the two analog I2C_SCLK and I2C_SDA ports that interface to the SYSMON component.
How can I work around this issue?
To work around this issue, close and reopen the checkpoint of the design, after the design has been fully linked with the reconfigurable module for the Update Region.
This issue could affect any designs using PCIe Tandem with Field Updates. It is scheduled to be fixed in a future release of the Vivado software.