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AR# 66807

Xilinx HSSIO Solution Center - Design Assistant Debugging Loopback Problems

Description

This answer record offers some basic debugging tips for Loopback.

Note: This answer record is part of the Xilinx HSSIO Solution Center (Xilinx Answer 37181). The Xilinx HSSIO Solution Center is available to address all questions related to HSSIO.

Whether you are starting a new design or troubleshooting a problem, use the HSSIO Solution Center to guide you to the right information.

Solution

The Xilinx GTs provide various loopback modes to test out the various paths of the transceiver on both TX and RX side. This can be used with either user data or with the internal PRBS generator and checkers in the GTs to validate the test path.

The loopback test modes fall into two broad categories - near-end loopback modes where the TX data is looped back closest to the traffic generator and the far-end loopback modes where the data is looped back at the far end of the link.

Refer to the Xilinx transceiver user guides (UG476/UG482 for 7 Series and UG576/UG578 for UltraScale and UltraScale+) "Loopback" section under Chapter 2 - Shared Features for complete details on the various loopback modes available.

When switching between loopback and normal modes please be aware that an RX reset (GTRXRESET) is required after entering and exiting near-end PMA loopback or far-end PMA loopback. The loopback modes are typically enabled through the LOOPBACK[2:0] port.

The following answer records provide some additional information regarding loopback modes:

(Xilinx Answer 47328)
(Xilinx Answer 53107)
(Xilinx Answer 64062)
(Xilinx Answer 65719)
AR# 66807
Date Created 03/10/2016
Last Updated 04/15/2016
Status Active
Type Solution Center
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
  • More
  • Kintex UltraScale
  • Virtex UltraScale
  • Less