We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 66905

UltraScale Soft Error Mitigation (SEM) IP – SSI device status_heartbeat timing violation


I am receiving a warning in Vivado that my design did not meet timing:

WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

The timing report shows the following failure:

Slack (VIOLATED) :        -0.091ns  (required time - arrival time)
  Source:                 example_support_wrapper/example_support/slr1_example_cfg/cfg_frame_ecce3/ICAPTOPCLK
                            (rising edge-triggered cell FRAME_ECCE3 clocked by clk  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            slr1_heartbeat_cnt_reg[16]/R
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@2.500ns period=5.000ns})


The signal status_heartbeat[n:0] (where n is equal to the number of SLRs in the device) must be registered before it is used in creating the heartbeat timeout logic.

AR# 66905
Date Created 03/28/2016
Last Updated 04/13/2016
Status Active
Type General Article
  • Vivado Design Suite - 2016.1
  • Soft Error Mitigation