We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Internet Explorer 11,
Safari. Thank you!
AR# 66906: UltraScale Soft Error Mitigation (SEM) IP – [DRC 23-20] Rule violation (PDCN-1569) LUT equation term check
UltraScale Soft Error Mitigation (SEM) IP – [DRC 23-20] Rule violation (PDCN-1569) LUT equation term check
In Designs which include SEM IP, the following DRC violation might be reported:
[DRC 23-20] Rule violation (PDCN-1569) LUT equation term check - Used physical LUT pin 'A1' of cell example_support_wrapper/example_support/sem_controller/inst/controller/controller_picocpu/alu_decode1_lut/LUT5 (in example_support_wrapper/example_support/sem_controller/inst/controller/controller_picocpu/alu_decode1_lut macro) is not included in the LUT equation: 'O5=((~A3)*A4*(~A5))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
Version Found: 2016.1
Version Resolved: N/A
This DRC rule violation can be safely ignored. The UltraScale and UltraScale+ designs have been tested in hardware without any observed anomalies.