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AR# 66906

UltraScale Soft Error Mitigation (SEM) IP – [DRC 23-20] Rule violation (PDCN-1569) LUT equation term check

Description

In Designs which include SEM IP, the following DRC violation might be reported:

[DRC 23-20] Rule violation (PDCN-1569) LUT equation term check - Used physical LUT pin 'A1' of cell example_support_wrapper/example_support/sem_controller/inst/controller/controller_picocpu/alu_decode1_lut/LUT5 (in example_support_wrapper/example_support/sem_controller/inst/controller/controller_picocpu/alu_decode1_lut macro) is not included in the LUT equation: 'O5=((~A3)*A4*(~A5))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.

Solution

Version Found: 2016.1

Version Resolved: N/A

This DRC rule violation can be safely ignored.  The UltraScale and UltraScale+ designs have been tested in hardware without any observed anomalies.

AR# 66906
Date Created 03/28/2016
Last Updated 04/13/2016
Status Active
Type General Article
Devices
  • Virtex UltraScale+
  • Kintex UltraScale+
IP
  • Soft Error Mitigation