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AR# 6691

LogiCORE PCI 64/66 FPGA Express - VHDL-2040 Warnings regarding unsupported attributes

Description

General Description: 

When I analyze the PCI files for the 64/66 Virtex/Virtex-E core, numerous warnings appear in the console regarding a number of unsupported attributes (the examples shown here are in FPGA Express):  

 

Warning: Attribute syn_edif_bit_format not supported for synthesis on line 117 (VHDL-2040) 

Warning: Attribute syn_edif_scalar_format not supported for synthesis on line 118 (VHDL-2040) 

Warning: Attribute syn_edif_bit_format not supported for synthesis on line 783 (VHDL-2040) 

Warning: Attribute syn_edif_scalar_format not supported for synthesis on line 784 (VHDL-2040) 

Warning: Attribute black_box not supported for synthesis on line 785 (VHDL-2040) 

Warning: Attribute syn_noclockbuf not supported for synthesis on line 104 (VHDL-2040) 

Warning: Attribute syn_edif_bit_format not supported for synthesis on line 105 (VHDL-2040) 

Warning: Attribute syn_edif_scalar_format not supported for synthesis on line 106 (VHDL-2040) 

Warning: Attribute syn_edif_bit_format not supported for synthesis on line 51 (VHDL-2040) 

Warning: Attribute syn_edif_scalar_format not supported for synthesis on line 52 (VHDL-2040)

Solution

In the newest versions of the PCI core, all the flows stem from the same source files. Where previously there were directories for FPGA Express, FC, etc., there is now only one directory for VHDL and one for Verilog.  

 

The attributes in question are for the Synplicity flow, and will produce warnings both in FC and FPGA Express. They can be safely ignored.

AR# 6691
Date Created 08/21/2007
Last Updated 05/14/2014
Status Archive
Type General Article