UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - All Programmable
  2. Support
  3. AR# 66918: Vivado Synthesis - Partial assignments to generic arrays in component map are not handled correctly

AR# 66918

Vivado Synthesis - Partial assignments to generic arrays in component map are not handled correctly

Description

When generic mapping is done element by element on an array as follows, I see incorrect logic in the synthesized netlist.

Vhd_Example_Level1 : example_design_level1
  GENERIC MAP (
  my_generic(0) => '0',
 my_generic(1) => '1',
  ......
  )

Solution

Partial assignments in generic mapping is an unsupported feature.

Use the following syntax instead:

Vhd_Example_Level1 : example_design_level1
  GENERIC MAP (
  my_generic => ('1' , '0'),
  ......
  )
AR# 66918
Date 06/13/2017
Status Active
Type Known Issues
Tools
  • Vivado Design Suite
Page Bookmarked