When synthesizing VHDL that has an entity with a port defined as a record, and one of the elements of the record is a vector of size 0, the whole port is ignored during Synthesis.
The following warning message is given:
Is this incorrect behavior?
This is expected behavior with the current implementation for handling null ports.
If an element of a record is null then the whole record is considered null.
It is recommended to avoid using a null vector in the record.