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AR# 66937

DDR4 and DDR3 IP - UNISIM simulations fail when using Self Refresh and Self Restore options

Description

Version Found: v2.0

Version Resolved: See (Xilinx Answer 58435)

When running a DDR4 or DDR3 IP behavioral simulation with Self Refresh and Self Restore enabled, an error message similar to the following might be seen:

DDR4 Error Message:

# sim_tb_top.instance_of_rdimm_slots[0].u_ddr4_rdimm_wrapper.rcd_enabled.genblk1.u_ddr4_dimm.rank_instan
ces[0].even_ranks.u_ddr4_rank.Micron_model.instance_of_sdram_devices[8].
micron_mem_model.u_ddr4_model.<protected>.<protected>:VIOLATION: cmdPPDE BG:0 B:0 A:0 (BL:8 WL:12 RL:14) @2238687 Required:
# tMOD + PL + CAL - 24 clocks.
# tMRSPDENc (+ CAL) - 24 clocks.

DDR3 Error Messages:

sim_tb_top.mem_model_x4.memRank[0].memModel[0].u_ddr3_x4.reset: at time 0.0 ps ERROR: CKE must be inactive when RST_N goes inactive.
sim_tb_top.mem_model_x4.memRank[0].memModel[0].u_ddr3_x4.reset: at time 0.0 ps ERROR: CKE must be maintained inactive for 10 ns before RST_N goes inactive.
sim_tb_top.mem_model_x4.memRank[0].memModel[0].u_ddr3_x4: at time 0.0 ps ERROR: tIPW violation on CKE by 560.0 ps

Solution

This specific issue only occurs when using the UNISIM models for simulation and is an issue with the MICRON model. Data integrity checks still pass. This issue can be safely ignored until the memory model is fixed.

Revision History:

04/16/2016 - Initial Release

AR# 66937
Date Created 03/31/2016
Last Updated 10/13/2016
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale