My design fails to meet timing with hold violations for the MII to RMII core. The MII to RMII IP core has a local clock which has a fan out of 614 or more.
The IP needs to change its clock path structure such that it can drive more fanout with lesser clock skew to avoid the hold time violation.
In Vivado 2016.1, a BUFG or BUFH option is added to the RX and TX output clock path.
This will fix the hold time violation issue.