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AR# 66942

LogiCORE MII to RMII v2.0 - Design fails to meet timing with hold violation for MII to RMII core


My design fails to meet timing with hold violations for the MII to RMII core. The MII to RMII IP core has a local clock which has a fan out of 614 or more.

CKLD #1 Warning Clock net z_system_combined_i/mii_to_rmii_0/U0/rmii2mac_rx_clk is not driven by a Clock Buffer and has more than 512 loads. Driver(s): z_system_combined_i/mii_to_rmii_0/U0/rmii2mac_rx_clk_reg/Q

The IP needs to change its clock path structure such that it can drive more fanout with lesser clock skew to avoid the hold time violation.



In Vivado 2016.1, a BUFG or BUFH option is added to the RX and TX output clock path.

This will fix the hold time violation issue.

AR# 66942
Date 04/05/2016
Status Active
Type General Article
  • Zynq-7000
  • Zynq UltraScale+ MPSoC
  • Artix-7
  • More
  • Kintex UltraScale
  • Kintex UltraScale+
  • Kintex-7
  • Virtex-7
  • Less
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