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AR# 66988

UltraScale Architecture PHY for PCI Express - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues for the UltraScale Architecture PHY for PCI Express Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express

Solution

Supported devices can be found in the following three locations:

  • Open the Vivado tool -> IP Catalog, right-click on the IP and select Compatible Families.
  • For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core Version Vivado Tools Version
v1.0 (Rev6) 2017.3
v1.0 (Rev5) 2017.2
v1.0 (Rev4) 2017.1
v1.0 (Rev3) 2016.4
v1.0 (Rev2) 2016.3
v1.0 (Rev1) 2016.2
v1.0 2016.1

 

Known and Resolved Issues

The following table provides known issues for the UltraScale Architecture PHY for PCI Express core, starting with v1.0, initially released in Vivado 2016.1.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record Title Version Found Version Resolved
NA NA
NA  

 

Other Information:

  • NA

Revision History:

04/13/2016 Initial release
08/06/2016 Updated for 2016.2 Release
10/05/2016 Updated for 2016.3 Release
01/24/2017 Updated for 2016.4 Release
04/05/2017 Updated for 2017.1 Release
AR# 66988
Date 10/23/2017
Status Active
Type Release Notes
IP
  • PCI-Express (PCIe)
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