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AR# 66988

UltraScale Architecture PHY for PCI Express - Release Notes and Known Issues


This answer record contains the Release Notes and Known Issues for the UltraScale Architecture PHY for PCI Express Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express


Supported devices can be found in the following three locations:

  • Open the Vivado tool -> IP Catalog, right-click on the IP and select Compatible Families.
  • For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Changes in v1.0 (Rev4)

  • Bug Fix
    • Updated the cpll cal counters as per the frequency of the reference clock selected
  • Other
    • Revision change in one or more subcores

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools Version
v1.0 (Rev4)2017.1
v1.0 (Rev3)2016.4
v1.0 (Rev2)2016.3
v1.0 (Rev1)2016.2

Known and Resolved Issues

The following table provides known issues for the UltraScale Architecture PHY for PCI Express core, starting with v1.0, initially released in Vivado 2016.1.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved

Other Information:

  • NA

Revision History:

04/13/2016Initial release
08/06/2016Updated for 2016.2 Release
10/05/2016Updated for 2016.3 Release
01/24/2017Updated for 2016.4 Release
04/05/2017Updated for 2017.1 Release
AR# 66988
Date 04/19/2017
Status Active
Type Release Notes
  • PCI-Express (PCIe)