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AR# 66993

2016.1 - compile_simlib - RAM64X8SW VHDL model not getting compiled by compile_simlib


After compiling simulation libraries in Vivado 2016.1 for my Third Party Simulator, I notice that the new RAM64X8SW VHDL model is not getting compiled.

However the Verilog model does get compiled. Is there a known limitation in the 2016.1 release?


There is a known limitation with the VHDL model with respect to compile_simlib. It is fixed in the 2016.2 release.

The work-around is to use the Verilog model. Please specify -L unisim_ver in your simulation script where it applies.

AR# 66993
Date 07/05/2016
Status Active
Type General Article
  • Vivado Design Suite
  • Vivado Design Suite - 2016.1
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