UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 66993

2016.1 - compile_simlib - RAM64X8SW VHDL model not getting compiled by compile_simlib

Description

After compiling simulation libraries in Vivado 2016.1 for my Third Party Simulator, I notice that the new RAM64X8SW VHDL model is not getting compiled.

However the Verilog model does get compiled. Is there a known limitation in the 2016.1 release?

Solution

There is a known limitation with the VHDL model with respect to compile_simlib. It is fixed in the 2016.2 release.

The work-around is to use the Verilog model. Please specify -L unisim_ver in your simulation script where it applies.

AR# 66993
Date Created 04/07/2016
Last Updated 07/05/2016
Status Active
Type General Article
Tools
  • Vivado Design Suite
  • Vivado Design Suite - 2016.1