This answer record contains known issues for Vivado Design Suite 2016.x related to IP core flows, including IP customization, IP generation, IP Packager, IP Catalog and integration of IP cores into the Vivado design environment.
Outstanding Known IP Flow Issues in Vivado 2016.3
(Xilinx Answer 60195) Editing a packaged IP in IP Packager and then discarding those edits might not completely remove all HDL file edits (Xilinx Answer 66285) XSDB message: Cannot stop MicroBlaze. Stalled on instruction fetch (Xilinx Answer 66982) The Customization GUI of IP offer connection(s) to board components that have already been used in a project (Xilinx Answer 66984) BRAM memory initialization in a user IP gives, "Critical Warning: [Synth 8-4445] could not open $readmem data file '32x16_rom_init.mem' "
(Xilinx Answer 67850) Validating an IP Iintegrator block design gives ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified (Xilinx Answer 67895) Packaging a BD design that contains a processer, using the "Use Generated Files" option, leads to invalid scoping of constraints (Xilinx Answer 68010) The out of Context (OOC) runs for a Block Design (BD) go out of date as soon as any Block configuration changes Known IP Flow Issues Resolved in Vivado 2016.3
(Xilinx Answer 67231) Implementing a Block Design (BD) project containing an XDMA MicroBlaze fails when using OOC per BD for generated BD outputs (Xilinx Answer 67235) IP pointing to XPM macros in Vivado 2016.1/2 break existing Non-project scripts (Xilinx Answer 67621) Invalid error issued when upgrading a Clocking Wizard IP core (Xilinx Answer 67986) Block Diagram OOC runs disappear from view after refreshing changed modules Known IP Flow Issues Resolved in Vivado 2016.2
(Xilinx Answer 67918) The Tools -> Report -> Report IP Status menu selection is missing in Vivado 2016.1 (Xilinx Answer 67984) - Upgrading an IP core beyond 2 major software versions results in an unexpected error Known IP Flow Issues Resolved in Vivado 2016.1
(Xilinx Answer 66114) ERROR: [BD 41-237] Bus Interface property DATA_WIDTH does not match between /axi_mem_intercon/m01_couplers/auto_pc/S_AXI(32) and /axi_mem_intercon/m01_couplers/auto_cc/M_AXI(512) (Xilinx Answer 64051) UltraScale MIG ELF file is not correctly populated when using Non-project mode (Xilinx Answer 66286) DisplayPort TX Subsystem IP errors in Generating Outputs : ERROR: [BD 41-1273] Error running post_propagate TCL procedure: invalid command name "::bd::addr::get_addresses_of" in managed IP project (Xilinx Answer 66291) AXI 10g Ethernet Example Design created from IPI AXI 10g Ethernet block fails in OOC generation with ERROR: [Synth 8-439] module 'bd_0_ten_gig_eth_pcs_pma_0' not found (Xilinx Answer 66292) Sub-core reference is not updated for migrated project even though the parent IP core was upgraded (Xilinx Answer 66395) Creating an example design for the GT Wizard IP instance gives: [Common 17-69] Command failed: ERROR:HACGExampleFork: Invalid script name specified (Xilinx Answer 66403) Video Processing Subsystem IP core in a Block Design does not fully generate the first time (Xilinx Answer 66407) Generating Output products (OOC per IP) on a hierarchical IP fails with [exportsim-Tcl-66] failed to open file to write (export_sim_options.cfg)
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