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AR# 66996

2016 Vivado - Vivado User Interface (GUI) and Project Management Known Issues


This answer record contains a list of Vivado Design Suite graphical user interface and project management known issues for Vivado IDE 2016.x.


Outstanding Known Issues in Vivado Design Suite 2016.3

(Xilinx Answer 53243)Replace File" directory browser does not update "Date Modified" field
(Xilinx Answer 55052)Vivado does not preserve XDC wildcards in generated Design Check Point (DCP)
(Xilinx Answer 55418)Message suppression rules are not editable
(Xilinx Answer 58937)Simulating IP core generated files gives: ERROR: [XSIM 43-3225] Can not find design unit work.<IP core TB> in library work located at xsim.dir/work
(Xilinx Answer 66827)Code Editor shows gargled text for long lines on RHEL 7.1 OS
(Xilinx Answer 66978)Implementation log file (.vdi) in the reports view gets overwritten if Generate Bitsream is rerun

Known Issues Resolved in Vivado 2016.3

(Xilinx Answer 66986)PDF file created with "Save as PDF' in Block Design does not show RTL logos for blocks in the design
(Xilinx Answer 66816)Code Editor does not change font of Text with syntax errors based on Tool preferences
(Xilinx Answer 67499)Loading a synthesized or implemented design in Vivado gives an Internal Exception and the error message "Xgd File 'xc****.xgd' is missing"
(Xilinx Answer 67915)Deleting a PBLOCK which contains objects selected in an open Timing window causes internal Exception

Known Issues Resolved in Vivado 2016.2

(Xilinx Answer 66985)Launching Vivado on a remote CentOS machine opens an X11 xterm instead
(Xilinx Answer 67917)(UG888) Tcl script hangs when run from the Text Editor

Known Issues Resolved in Vivado 2016.1

(Xilinx Answer 64191)CRITICAL WARNING: [Pfi 67-14] Hardware Handoff if original location of .hwdef file is not found
(Xilinx Answer 65564)Mem file not copied to simulation directory - ERROR: [VRFC 10-451] cannot open file 'int_infile
(Xilinx Answer 66967)Exporting simulation files for Questa simulator generates files for all supported simulation tools
(Xilinx Answer 66968)Write_debug_probes command is not issued if opt_design is disable
(Xilinx Answer 67236) - Tcl regular expression syntax for filter function changed to BOOST

AR# 66996
Date Created 04/07/2016
Last Updated 10/13/2016
Status Active
Type Known Issues
  • Vivado Design Suite - 2016.1
  • Vivado Design Suite - 2016.2
  • Vivado Design Suite - 2016.3