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AR# 67041

Soft Error Mitigation (SEM) IP - Using UltraScale SEM IP in Vivado IP Integrator (IPI)


UltraScale SEM IP has some differences when generated from the Vivado IP catalog and the IP Integrator catalog. 

What are these differences? How is UltraScale SEM intended to be used in IP Integrator?


Monolithic UltraScale devices:

UltraScale SEM IP for monolithic devices is supported in IP Integrator with some limitations. These limitations are apparent when configuring the IP from IP Integrator.

  • The mode option is fixed to mitigation_and_testing without error classification.
  • The structural option to select the hierarchy for the ICAP and FRAME_ECC primitives is fixed.

To create a functional SEM solution on the IP canvas, these primitives are included within the SEM controller DCP. As a result, the ICAP cannot be shared with other applications such as Partial Reconfiguration.

Refer to (PG187), Customizing and Generating the Core for more information about the available configuration options using the Vivado IP catalog.


Starting in Vivado 2016.1, an Add Module feature will enable the user to pull the SEM example design HDL onto the IP Integrator canvas, if desired.

SSI UltraScale devices:

UltraScale SEM IP for SSI devices is not supported in IP Integrator. The UltraScale SEM solution requires a separate SEM controller and configuration primitives (ICAP and FRAME_ECC) on each SLR, and this is not easily achieved in IP Integrator automatically.

If targeting SSI devices, it is required that SEM customers use the standard HDL flow to generate the IP.

Generate the SEM IP from the Vivado IP catalog as described in (PG187).

Open the example design, which demonstrates the proper way to constrain and instantiate the controller, configuration primitives, and helper blocks for an SSI device.

AR# 67041
Date 01/20/2017
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale