Version Found: v2.0
Version Resolved: See (Xilinx Answer 58435)
Targeting the following list of DDR4 3DS RDIMMs and LRDIMMs in Vivado 2016.2 and earlier generates two sets of CK/CK# clock pairs. However, their data sheets show the CK pair is terminated but not used.
You can leave the extra CK/CK# clock pair connected to the 3DS RDIMM as it is terminated but not used.
Starting in Vivado 2016.2, the DDR4 IP will generate only 1 CK/CK# for the DDR4 3DS RDIMM part M393A8K40B21-CTC
The following message is displayed in the ip_upgrade.log file:
These messages are safe to ignore. Update the top level wrapper and XDC to match the port width change.
04/18/2016 - Initial Release
07/05/2016 - Revised to include more parts for Vivado 2016.3