Is it possible to connect an ILA core to the signals coming from or going to the peripherals on the Zynq PS7 if the output is routed to the multiplexed I/O pins (MIO or FIXED_IO) so that the output or bidirectional traffic can be analyzed?
Because the ILA and VIO cores reside in the Zynq PL (fabric), the output signals from the peripheral must have a routing path from the peripheral onto the fabric.
If the peripheral is mapped to the multiplexed I/O pins (MIO) then there is no path for these signals to get to the fabric and to be probed by an ILA or VIO which reside in the PL.
The tools will allow the MIO or FIXED_IO to have MARK_DEBUG set TRUE, however they will issue the warning below during synthesis:
These signals can be probed by an ILA or VIO core if the output is moved from the MIO bus to the EMIO bus which allows a path to the PL fabric, however the peripheral's output will no longer route to the MIO pin.
This requires a pinout change, as the signals will pass through the fabric and can be probed on the way to a SelectIO pin accessible from the PL.
The paths to either MIO or EMIO are shown below in figure 2-3 from the Zynq-7000 TRM (UG585):
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