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AR# 67083

2016.1 - Vivado IP Integrator - How to Package a MicroBlaze Block Design containing an ELF


This Answer Record will show the complete flow to package a MicroBlaze Block Design (BD) with an ELF.


Step 1: Create the MicroBlaze Block Design

The MicroBlaze system used in this demo is seen below:


If you are using a board file, then make sure that Board Interface is set to custom for IP that have external ports. 

For example, I have to do this for the GPIO, Clk Wiz and the Reset Module.

Once this is done, Generate Output Products, Create HDL wrapper, and export to SDK (File -> Export -> Export Hardware):


Next launch SDK (File -> Launch SDK)

Step 2: Create the SDK application:

In the SDK, I created a simple GPIO application (File -> New -> Application Project):


Select the Peripheral Test App template:


There are precompiler options that can be passed to the test peripheral application if the user wants to test in Simulation. 

This can be seen below:


This is done to add a delay so that the LED is visible. However, in simulation, this is not required. 

So, we can create a simulate ELF with the precompiler options added. 

To add this, right click on the application and select C/C++ Build Settings. You can pass a symbol as shown below:


You should now have two ELF files; one with the pre-compiler, and the other without.

Note: You will need to compile one with this precompiler option and one without to generate the two ELF files.

Once these are built (Select Project -> Build Project if this does not build automatically) exit SDK and return to the Vivado project.

Step 3: Add ELF(s) to Vivado:

Right click on Design Sources -> Add Sources, and Add or create design sources:

Navigate to the ELF in the SDK workspace that was created in the previous step and add it.

Repeat this for the Simulation Sources:

The Design Sources should look like the following:

Next, we need to Associate the ELF. Select Tools -> Associate ELF:


Note: Users do not have to use different ELF files. They can use the same ELF for simulation and implementation.

Step 4: Create Package BD:

Tools -> Create and Package IP and select Package a block design in the Packaging Options:

Select the location where you want the IP to be located, and tick the "Include .xci files" box and then Next to continue:


Note: you will get the following warning:

This will be covered later.

Select Capability -> Add -> Add Family Explicitly:


Here, I have chosen all the Families. However, you can limit this to your target devices. 

This will determine if the IP shows in the IP catalog based on the device selected in the Vivado project:


Note: the IP File properties are populated with the SCOPED_TO_REF and SCOPED_TO_CELLS properties:


Once you are satisfied here, select Review and Package and Package IP.

Step 5: Add Packaged BD to a new Block design:

Create a new Vivado Project. In the IP Catalog, add the packaged BD:


Add the packaged BD to your Block design.

Note: Do not use the same name for the BD as you did for the packaged BD or you will see issues in synthesis.

Step 6: Verify that ELF data is populated into the block RAM:

Run Synthesis or Implementation and open the synthesized/implemented design, then use Ctrl + F to search for all BRAM in the project.

This will list all of the BRAM used. You can then select one of the BRAM used in the packaged IP:


Select one of the BRAM, and you should see the cell properties INIT_00 populated with data:


Step 7: Simulate the packaged BD:

Note: running step 6 is not critical for this step.

Run the command below in the Tcl console to create the Testbench for the BD:

  • tclapp::xilinx::designutils::write_ip_integrator_testbench -addToProject

Note: There is a known issue in Vivado 2016.1 where the Synthesis ELF will over-write the Simulation ELF. 

If these are the same, you will not see any problems. If you want to Simulate another ELF file, you will need to add the ELF as a simulation source:

You will need to manually set the SCOPED_TO_CELLS, and SCOPED_TO_REF properties for the Simulation ELF file.

The SCOPED_TO_REF is the BD name. In this example, the SCOPED_TO_REF property on the gpio_sim.elf is my_bd

The SCOPED_TO_CELLS is the path to the MicroBlaze cell. 

For example:

If the Target Language is set to VHDL, this is design_1_0//U0/microblaze_0

If the Target Language is set to Verilog, this is design_1_0/inst//microblaze_0

To set the properties, highlight the simulation ELF, and in the Properties tab enter the SCOPED_TO_CELLS and SCOPED_TO_REF values:


Once this is done, you can Run Simulation.

Note: If the properties detailed above are not set correctly, you will see a warning in Vivado Simulator.

The Synthesis ELF will be used instead of the Simulation ELF. 

You can also see the path in the simulated design that can be used to set the SCOPED_TO_REF:


If I run the simulation, I can see that the gpio_sim.elf was run, as the LEDs toggle quite quickly.

Therefore I can conclude that the delay was not added:


AR# 67083
Date Created 04/22/2016
Last Updated 05/18/2016
Status Active
Type General Article
  • Vivado Design Suite - 2016.1