Version Found: 2016.1
When using a PLL Clock Source as Fabric (Driven by BUFG) the following error might occur:
Note: this Answer Record should not be viewed in isolation. For all other known issues and to see what version of Vivado / the High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)
The PLL and BITSLICE_CONTROL must be placed in the same clock region. The input to the PLL can come from another clock region if the PLL CLK Source is set to BUFG, however this is sub optimal so you must set the CLOCK_DEDICATED_ROUTE FALSE in the .xdc file.
Example of constraints for the XDC :