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AR# 67105

High Speed SelectIO Wizard - ERROR: [Place 30-693] Unroutable Placement! PLL / BITSLICE_CONTROL component pairs are not placed in a routable site pairs.

Description

Version Found: 2016.1

When using a PLL Clock Source as Fabric (Driven by BUFG) the following error might occur:

ERROR: [Place 30-693] Unroutable Placement! PLL / BITSLICE_CONTROL component pairs are not placed in a routable site pairs. The PLL and it is load BITSLICE_CONTROLs need to be placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.

 

 

 

 

Note: this Answer Record should not be viewed in isolation. For all other known issues and to see what version of Vivado / the High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)

Solution

The PLL and BITSLICE_CONTROL must be placed in the same clock region. The input to the PLL can come from another clock region if the PLL CLK Source is set to BUFG, however this is sub optimal so you must set the CLOCK_DEDICATED_ROUTE FALSE in the .xdc file.

Example of constraints for the XDC :

set_property LOC PLLE3_ADV_X0Y6 [get_cells RX_Side/inst/top_inst/clk_rst_top_inst/clk_scheme_inst/GEN_PLL_IN_IP_US.plle3_adv_pll0_inst]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets IBUFDS_inst/O]

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
64216 High Speed SelectIO Wizard - Known Issue list N/A N/A
AR# 67105
Date Created 04/26/2016
Last Updated 06/24/2016
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale