We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 6713

Virtex - What is the recommended way to set or reset FFs in a Virtex design? Do I still need to use STARTUP_VIRTEX block?


For HDL designs, what is the recommended way to asynchronously reset or set flip-flops in a Virtex design? Is it still necessary to use the STARTUP_VIRTEX block?


The recommended method for asynchronously resetting or setting FFs in Virtex designs is to write this high fanout reset/set signal explicitly in the HDL codes and not use the STARTUP_VIRTEX block. There are two advantages to this:

1. This method gives you a lower skew. The reset/set signal will be routed on to the secondary long lines in the device, which are global lines with minimal skews. Using the GSR of the Startup Block potentially leads to a skew problem that can put a design in an unknown state. Since Virtex is rich in routings, our software can easily place and route this signal on the global lines.

2. Our TRCE program will analyze the delays of this explicitly written reset/set signal. Users can read the .twr file (report file of the TRCE program) to find out exactly how fast its speed is and how big the skew is. TRCE does not analyze the delays on the GSR net of the STARTUP_VIRTEX block.

It is not necessary to use the STARTUP_VIRTEX block if the reset/set signal is explicitly coded. However, users still have the option of using STARTUP_VIRTEX if they choose to, and if the GSR skew is not a concern.

To see an example of how to infer a register with a set/reset signal, please refer to the 4.1i software manual:

-> Synthesis and Simulation Design Guide -> Chapter 3 , General HDL Coding Style -> Using Preset Pin or Clear Pin.

AR# 6713
Date Created 08/21/2007
Last Updated 12/15/2012
Status Active
Type General Article