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AR# 67144

UltraScale+ PCI Express Integrated Block (Vivado 2016.1) - Incorrect GT Quad Location for Virtex 9P Devices


Version Found: v1.1 (Vivado 2016.1)

Version Resolved and other Known Issues: (Xilinx Answer 65751)

The GT Quad locations that are shown in the core configuration GUI for Virtex 9P-flgb2104 are 5 quads higher than it actually is in implementation.

For example, when GTY 229 is selected in the GUI, the design will use GTY 224. The GT locations used in implementation is correct and the issue is only in the core configuration GUI.


This is a known issue to be fixed in a future release of the core. To resolve the issue, please install the patch attached to this answer record as described below.

  • The provided patch is for Vivado 2016.1 for the UltraScale+ PCI Express Integrated Block core.
  • Unzip the attached zip file to the directory of your choice.
  • Open Vivado 2016.1 and create a new project.
  • Open IP catalog. Right click the core you are using and choose IP Settings.
  • Click Add Repositories and point it to the location where you have unzipped the patch.
  • Click OK and you are now ready to generate the core.
  • If you have previously generated the core, you can choose 'Upgrade IP' on your core.
  • Alternatively, you can use the MYVIVADO environment variable and point this to the location of the patch.

After the patch is installed, the version of the UltraScale+ PCI Express Integrated Block core should indicate: v1.0 (Rev. 67144).

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History

05/14/2016 - Initial release


Associated Attachments

Name File Size File Type
AR67144_Vivado_2016_1_preliminary_rev1.zip 723 KB ZIP
AR# 67144
Date Created 05/02/2016
Last Updated 05/16/2016
Status Active
Type Known Issues
  • UltraScale+ FPGA Integrated Endpoint Block for PCI Express