We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 6718

A1.5/F1.5 RAM16X1D Dual port RAM: Doing a read on the dpra port reads an 'X' when the clock not defined, even though this is an async read RAM


Keywords: RAM, X, second port, port B, dual port, asynce read

Urgency: Standard

General Description:

I am using the RAM16X1D, and in simulation I am seeing X when doing a read
on the dpra port. I have the write address (a3 to a0) at a known value, the
write enable is low, but I the clock is undefined.

Shouldn't I be able to do a read on the dpra port even though the clock is


This is a VHDL simulation model problem that is will be fixedd in the
next release of the Xilinx software.

Currently during simulation if a read operation is to be performed then
the user must ensure that all inputs are at a known level.

This is fixed in 2.1i
AR# 6718
Date Created 08/31/2007
Last Updated 10/05/2008
Status Archive
Type General Article