In the case of a secondary CPRI core which is using shared clocking resources from a primary CPRI core, a software reset (bit 31 of General Configuration and Transmit Alarms register) of the secondary CPRI core will not be cleared on read back of the register.
This applies to Vivado versions 2015.1 up to 2016.1. CPRI v8.6 in 2016.2 has a fix incorporated.
For earlier versions the work-around is as follows:
Generate the secondary CPRI core with Additional Transceiver Control and Status Ports selected. The clk_ok_in signal to the core should be AND'd with the cores own output signal gt_txresetdone.
This will allow the software reset bit to clear after the CPRI core has completed its reset sequence.
For other CPRI known issues, please refer to (Xilinx Answer 54473)