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AR# 67219

Designs created with Vivado versions up to and including 2016.1 do not consistently apply the DIFF_TERM attribute appropriately. DRC and reporting of the attribute might not reflect its true status

Description

In UltraScale and UltraScale+ designs generated with Vivado versions up to and including 2016.1, the DIFF_TERM attribute is not reported appropriately, nor is the attribute properly checked to ensure that a valid bank voltage is used when the attribute is defined in the HDL as TRUE.

In these designs if DIFF_TERM is set to TRUE in the HDL, the IBUFDS or IOBUFDS instance will enable the internal termination, but will not trigger Design Rules Checks on the attribute, nor will the design or reports indicate the presence of internal termination. 

If a design resides in a 1.8V HP bank or a 2.5V HR bank (UltraScale only) on an LVDS input, there are no issues and the design will function with termination enabled even though the attributes presence is not detectable in the tools.

Solution

When DIFF_TERM is set to TRUE in the HDL, IBUFDS or IOBUFDS instance will enable the internal termination, but will not trigger all Design Rules Checks (DRC) on the attribute, nor will the design or reports indicate the presence of internal termination. 

The DRC that is missed can allow an LVDS input with DIFF_TERM enabled to reside in a bank, whose bank voltage is not supported. Having DIFF_TERM enabled in a bank will not cause damage provided the input voltage does not violate the Data Sheets Vin (I/O input voltage for I/O banks) Specification.

Typically DIFF_TERM will be applied in the design constraints file (XDC) and thus there are no issues. However, when the attribute is defined in the HDL the design might be operating in a mode that is not expected by the user:

 

  • If DIFF_TERM is ONLY defined in the HDL as TRUE, in a 1.8V HP bank or a 2.5V HR bank (UltraScale only) on an LVDS input, there are no issues and the design will function with termination enabled even though the attribute's presence is not detectable in the tools via property checks or I/O reports. Designs where termination exists both externally and internally could potentially be terminated twice.
    In this scenario there are no reliability concerns provided Vin in the data sheet is observed.
    Functionality is not expected to be substantially impacted due to robust receiver performance and driver margins, however it is recommended that these designs are re-implemented with the desired DIFF_TERM status applied in the XDC file.
  • If DIFF_TERM is ONLY defined in the HDL as TRUE, but the input resides in a bank whose voltage is not compatible with LVDS (1.8V HP bank or a 2.5V HR bank (UltraScale only)) it is recommended that the desired state of the DIFF_TERM attribute be applied to the XDC.
    Designs that are already implemented are expected to be functional and will not have reliability concerns provided the data sheet's VIN specification is adhered to.
    There are two possible consequences:
    1. Designs where termination exists both externally and internally could potentially be terminated twice. In this scenario there are no reliability concerns provided Vin in the data sheet is observed.
      Functionality is not expected to be substantially impacted due to robust receiver performance and driver margins, however it is recommended that these designs be re-implemented with the desired DIFF_TERM status applied in the XDC file.

       

       

    2. Designs where termination exists internally only, but in an unsupported bank voltage are not expected to have any compromised reliability provided Vin in the data sheet is adhered to.
      It is expected that interfaces in this scenario will not see any damage or degradation to the functionality observed over time, however it is recommended that this condition is remedied in future designs.
  • If DIFF_TERM is set to FALSE in the HDL, there are no issues and the reporting and implemented design will accurately reflect the state of DIFF_TERM.
  • If DIFF_TERM is defined in the XDC file (even if it is also defined in the HDL), the XDC constraint will accurately reflect the attribute's status and all relevant DRCs related to DIFF_TERM will be applied to the design.

Several IP cores, such as memory interface IP will leverage the HDL to define the DIFF_TERM properly, so a safe way to ensure the most complete design is to enable the attribute on all LVDS and DIFF_SSTL inputs in the XDC file.

 

As noted, defining DIFF_TERM via the XDC file will ensure the implementation tools operate correctly and will over-ride any attribute set in the HDL.

When internal differential termination is NOT desired use the following:

set_property DIFF_TERM_ADV TERM_NONE [get_ports LVDS_P_PORTNAME]

When internal 100ohm differential termination IS desired use the following:

set_property DIFF_TERM_ADV TERM_100 [get_ports LVDS_P_PORTNAME]
AR# 67219
Date Created 05/12/2016
Last Updated 07/04/2016
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Zynq UltraScale+ MPSoC
  • Virtex UltraScale+
  • Virtex UltraScale