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AR# 67231

2016.2 Vivado IP Flows - Implementing a Block Design (BD) project containing an XDMA MicroBlaze fails with ERROR: [Opt 31-38] IBUFDS_GTE2 (pin name) I pin is connected directly to a top-level port

Description

I have a project with an IP Integrator block design (BD) that contains instances of MicroBlaze, XDMA and MIG IP.

I have used designer assistance and board automation to assure that the pin connections were made properly for the board I am using.

Synthesis completes successfully, however Implementation fails in the design optimization phase with the following critical warnings and error.

CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, Illegal to place instance design_1_i/util_ds_buf_0/U0/USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUFDS_GTE2_I on site AB8. The location site type does not match the instance type. [/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0_board.xdc:3]
CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, Illegal to place instance design_1_i/util_ds_buf_0/U0/USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUFDS_GTE2_I on site AB8. The location site type does not match the instance type. [/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0_board.xdc:4]
.
ERROR: [Opt 31-38] IBUFDS_GTE2 design_1_i/util_ds_buf_0/U0/USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUFDS_GTE2_I I pin is connected directly to a top-level port. An IBUF must be inserted in between the port and the IBUFDS_GT
Resolution: Please check the input design and ensure that the specific pin is driven by an IBUF. Once the design is modified, then re-run the Vivado flow.
IBUFDS_GT.I is not connected to an IBUF

Looking at the "design_1_util_ds_buf_0_0_board.xdc" constraint file I see the following constraints:

set_property BOARD_PIN
{pcie_mgt_clkn}
[get_ports IBUF_DS_N]
set_property BOARD_PIN
{pcie_mgt_clkp}
[get_ports IBUF_DS_P]

It seems that the Out of Context (OOC) synthesis of the BD does not insert I/O buffers. Subsequently, the set_property commands which set physical constraints in IP XDC are not valid.

Should these OOC board constraints NOT be there in this case?

Solution

The problem has been seen with the XDMA IP on 7 Series (Virtex-7, Artix-7 and Kintex-7) designs when using the OOC per BD option to generate output products for a BD.

The project implements without issues if output products are generated with either the global synthesis or the OOC per IP option.

The problem occurs because of the following:

  1. The in_context.xdc for the BD puts a BUFFER_TYPE of NONE on the port.
    set_property -quiet CLOCK_BUFFER_TYPE NONE [get_ports -quiet pcie_refclk_clk_p]
  2. This correctly prevents Synthesis from inserting an IBUF during top level synthesis. 
  3. However, the constraint is not being removed for LOPT, which should insert the IBUF. 


This issue will be fixed in Vivado 2016.3.

To work around the issue in Vivado 2016.1 or 2016.2, do one of the following:


  • Generate BD output targets as OOC per IP
  • Generate BD output targets using the Global Synthesis option (No OOC synthesis)
  • Remove the IO_BUFFER_TYPE properties after Synthesis.
AR# 67231
Date Created 05/16/2016
Last Updated 12/02/2016
Status Active
Type Known Issues
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
Tools
  • Vivado Design Suite - 2016.1
  • Vivado Design Suite - 2016.2