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AR# 67253

UltraScale DDR4 - Starting with the release of Vivado 2016.1, both read and write Vref calibration is disabled.

Description

Starting with the release of Vivado 2016.1, both read and write Vref calibration is disabled. This answer record details why the stages have been safely disabled.

Solution

Through characterization, it has been determined that read and write Vref calibration are not required.

The eye sizes found with the default read/write Vref settings are as good as the eye sizes found with the calibrated read/write Vref values.

As these stages of calibration add calibration time and have been found to not have positive affects on the eye size, the stages have been disabled starting with the 2016.1 release.

If you would like to manually re-enable these stages, follow the steps below:

1) Follow the steps in (UG896) for modifying IP. See the "Editing IP Sources" section.

2) Open the "core_name/rtl/ip_top/core_name_ddr4.sv" in a text editor outside of Vivado.

3) Locate the following lines. Note, these lines will occur twice. Once under `ifdef SIMULATION and again under `else. You will need to modify the lines within the `else.

     parameter         CAL_RD_VREF               = "SKIP",
     parameter         CAL_RD_VREF_PATTERN       = "SIMPLE",
     parameter         CAL_WR_VREF               = "SKIP",
     parameter         CAL_WR_VREF_PATTERN       = "SIMPLE",

4) Modify the SKIP setting to full:

     parameter         CAL_RD_VREF               = "FULL",
     parameter         CAL_RD_VREF_PATTERN       = "SIMPLE",
     parameter         CAL_WR_VREF               = "FULL",
     parameter         CAL_WR_VREF_PATTERN       = "SIMPLE",

AR# 67253
Date Created 05/19/2016
Last Updated 05/26/2016
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale
Tools
  • Vivado Design Suite - 2016.1
IP
  • MIG UltraScale