We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 67254

Vivado 2016.1 write_bitstream: Issue configuring 7 Series SSIT designs when porting from 2015.4 to 2016.1


In Vivado 2016.1 write_bitstream, some optimization strategies were added for 7 Series SSIT devices which caused the clock that feeds the DCI matching state machine to get disconnected from the block.

The result is that DCI will not calibrate, which impacts on the effective termination, as well as potentially halting configuration for certain startup sequences.

This issue is specific to SSIT designs where there are unused tiles, such as the CFG_CENTER tile, in the Master and Slave SLRs.

The issue presents itself in Vivado 2016.1 with a failed configuration showing an End of Startup status.


The work- around is to set the following parameter via tcl.pre or in the Tcl console prior to running write_bitstream:

set_param bitgen.EvalUnusedTiles true

AR# 67254
Date 06/08/2016
Status Active
Type General Article
  • Virtex-7
  • Vivado Design Suite - 2016.1