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AR# 67258

LogiCORE IP MIPI D-PHY Controller v2.0 - Why is there a change to the rxvalidhs behavior when receiving in high-speed mode?


Why is there a change to the rxvalidhs behavior when receiving in high-speed mode?

(PG202) November 18, 2015 (MIPI D-PHY v1.0) states the following:

"rxvalidhs can go Low during high-speed reception due to FIFO latency in D-PHY RX".

However, (PG202) April 06, 2016 (MIPI D-PHY v2.0) states that rxvalidhs is now always high during high-speed reception.

Why was this changed and can the can rxvalidhs go low (0) during high-speed reception when using the MIPI D-PHY Controller v2.0?


No, the rxvaildhs will no longer go low '0' when using the MIPI D-PHY Controller.

This change is intentional and is captured in (PG202) with waveforms.

This is due to a change in the design of the MIPI D-PHY Controller:

  • MIPI D-PHY v1.0 was doing asynchronous reads from XiPHY FIFO and converting to PPI domain using Shallow fabric FIFO. Due to CDC and clock rate mismatch, rxvalidhs could go low during High-Speed data reception.
  • MIPI D-PHY v2.0 leverages the FIFO_WRCLK_OUT of XiPHY from the RX clock lane and eliminates the CDC requirements. There is no longer a FIFO in the RX Data path, so rxvalidhs will not go low in the MIPI D-PHY Controller v2.0.
AR# 67258
Date Created 05/22/2016
Last Updated 06/03/2016
Status Active
Type General Article
  • Virtex UltraScale+
  • Kintex UltraScale+
  • Zynq UltraScale+ MPSoC
  • Vivado Design Suite - 2016.1
  • MIPI D-PHY Controller