Why is there a change to the rxvalidhs behavior when receiving in high-speed mode?
(PG202) November 18, 2015 (MIPI D-PHY v1.0) states the following:
"rxvalidhs can go Low during high-speed reception due to FIFO latency in D-PHY RX".
However, (PG202) April 06, 2016 (MIPI D-PHY v2.0) states that rxvalidhs is now always high during high-speed reception.
Why was this changed and can the can rxvalidhs go low (0) during high-speed reception when using the MIPI D-PHY Controller v2.0?
No, the rxvaildhs will no longer go low '0' when using the MIPI D-PHY Controller.
This change is intentional and is captured in (PG202) with waveforms.
This is due to a change in the design of the MIPI D-PHY Controller: