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AR# 67307

UltraScale+ PCI Express Integrated Block (Vivado 2016.1) - Tactical Patch with various fixes

Description

Version Found: v1.1 (Vivado 2016.1)

Version Resolved and other Known Issues: (Xilinx Answer 65751)


In the tactical patch attached to this answer record, the following fixes have been implemented:

1. pcie_cq_np_req tied to 2b11 from the user logic in the Xilinx example design in AXIST 512-bit mode. This is required to return correct credits.
2. Fixed logic to make sure pcie_cq_np_req_count provides correct NP credit received count in AXIST 512-bit mode.
3. Fixed logic related to cfg_msg fix where transmit message interface incorrectly generates two messages instead of one.
4. Fixed (Xilinx Answer 67144) for flgc2104 and flga2577 packages.
5. GUI options updated for straddle mode in AXIST 512-bit.


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

Solution

These issues will be fixed in the next release of the core. Please install the patch in Vivado 2016.1 as described below:

METHOD 1:

  1. Navigate to the $XILINX_VIVADO/patches directory (create this directory if it does not exist)
  2. Extract the contents of the ".zip" archive to a directory starting with the name AR67307
    Note: most extraction tools will allow you to automatically create a directory with the same name as the zip file
  3.     c. Run Vivado software tools from the original install location.


METHOD 2:

  1.     a. Creating a separate directory containing patched files
        b. Extract the contents of the ".zip" archive to the desired patch directory location.
        c. Set the MYVIVADO environment variable to point to this patch directory
               i.e. set MYVIVADO=C:\MYVIVADO\vivado-patch-AR67307\vivado\
        d. Run Vivado software tools from the original install location.

Revision History:

06/20/2016 - Initial Release

Attachments

Associated Attachments

Name File Size File Type
AR67307_Vivado_2016_1_preliminary_rev1.zip 723 KB ZIP
AR# 67307
Date Created 06/01/2016
Last Updated 08/11/2016
Status Active
Type Known Issues
IP
  • UltraScale+ FPGA Integrated Endpoint Block for PCI Express