UltraScale and UltraScale+ MPSoC Evaluation Kits are fully compliant with the VITA 57.1 standard. This means that any FMC card that is used with these boards must have an EEPROM on board programmed according to the IPMI format defined in the VITA 57.1 FMC specification.
The IPMI specification notes that one should use a 2K EEPROM which is compatible with 24C02 devices. This EEPROM must be available to be queried at power on so that the appropriate VADJ voltage can be set on the carrier card.
If this specification is not followed, the VADJ voltage will not power up correctly (it will correctly remain at 0V). VADJ can be set manually through the FMC Menu of the System Controller on UltraScale and UltraScale+ MPSoC Kits.
UltraScale and UltraScale+ MPSoC Evaluation Kits adhere to the EEPROM IPMI format defined in the VITA 57.1 specification.
If a connected FMC card has a blank or corrupt EEPROM, the VADJ rail will not be enabled at power on. Evaluation Kits have the ability to override VADJ using the system controller UART menu.
Extreme caution is advised when following this method.
1) Connect to the System Controller through the USB UART interface on the Evaluation Kit (choose the Enhanced COM port, Baud rate 115200).
2) In the terminal program (for example, TeraTerm), under the 'Setup' tab, open 'Serial Port' and select: Baud Rate 115200, Data 8 bit, No Parity, Stop 1 bit and Flow Control None. Click OK.
4) Select '4. Adjust FPGA Mezzanine Card (FMC) Settings'
|Boards & Kits||