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AR# 67320

Kintex/Virtex/Zynq UltraScale+ MPSoC: Incorrect GTH/GTY CPLL Frequency


The Kintex/Virtex/Zynq UltraScale+ MPSoC GTH/GTY transceiver CPLL might not be able to lock reliably after configuration or removing/re-applying the reference clock or asserting/de-assserting CPLLPD.

In the failure state, the CPLL might be stuck at an invalid output frequency and the CPLLLOCK signal might incorrectly be high.


For the UltraScale+ GTH/GTY CPLL to lock reliably, the CPLL calibration block should be used to ensure that the CPLL locks reliably and acquires the correct frequency.


The GT Wizard can generate this block automatically but this is not currently included by default and none of the GT Wizard based Parent IPs that use CPLL have this turned on in Vivado 2016.2 or Vivado 2016.3.

To turn on the CPLL calibration block in the Wizard, the work-around below should be followed.

This is planned to be enabled/turned on automatically by the Wizard in Vivado 2017.1 and this CPLL information will also be added to the UltraScale Architecture GTH/GTY Transceivers user guides (UG576 and UG578) in a future revision.


IP generation in batch mode:

During the IP Core generation, include the following Tcl command to the dict as part of the core generation.


set_property -dict [list CONFIG.INCLUDE_CPLL_CAL {1} ] [get_ips gtwizard_ultrascale_0]

IP generation in GUI mode:


If the IP is generated from the Vivado GUI, please follow the steps below.

1) Generate the GT wizard design

2) Run the following command in the Tcl console:

set_property -dict [list CONFIG.INCLUDE_CPLL_CAL {1} ] [get_ips gtwizard_ultrascale_0]

3) Select the GT wizard IP .xci file and reset the output products.

4) Generate the GT wizard design again.


This issue is due to be fixed in Vivado 2017.1.

AR# 67320
Date 11/21/2016
Status Active
Type General Article
  • Kintex UltraScale+
  • Virtex UltraScale+
  • Zynq UltraScale+ MPSoC
  • IO Interfaces
  • UltraScale FPGA Transceiver Wizard