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AR# 67330

Zynq UltraScale+ MPSoC - PS DDR Pin Swap Guidelines

Description

Which pins can be swapped on a Zynq UltraScale+ PS DRAM interface?

Solution

A byte lane includes any signals associated with the aligned 8-bits of DQ, such as DM, DQS, DQS_N, DBI and DQ signals.


LPDDR4

  1. Command/Address (CA) bits cannot be swapped.
  2. DQ byte lane swapping is not allowed in order to support CA training.
  3. DQ bit swapping within a byte lane is not allowed in order to support CA training.

DDR3

  1. Address/Command/Control bits cannot be swapped.
  2. DQ byte lane swapping is allowed.
  3. DQ bit swapping within a byte lane is allowed because DDR3 and DDR3L do not support the write CRC (Cyclic Redundancy Check) feature.


DDR4

  1. Address/Command/Control bits cannot be swapped.
  2. DQ swapping rule:
  • If not using the DDR4 Write CRC feature byte lanes can be swapped from the SoC -> SDRAM component in DDR4 mode and bits within a byte lane can be swapped without restriction.


DDR4 Write CRC


  • For Write CRC, the bit order must be 1:1 between the source (SoC) and destination (DRAM) component interfaces to ensure that both source and destination calculate the same CRC value. Write CRC computation is based on bytes.
  • DDR4 DRAM vendors can also swap pins on the DIMMs. Thus pin-swapping is not recommended when using DDR4 DIMMs with the write CRC feature.
  • Byte lanes cannot be swapped from the SoC -> DIMM connector in DDR4 mode if using the write CRC feature.
  • To compensate for pin swaps when using Write CRC, the PS DDR Controller must understand the bit order at the SDRAM to map the DQ bits into the CRC generator for WRITE commands so that the SDRAM decodes the CRC correctly.
    • To reduce the number of variations in DQ mapping, the following rules have been defined:
      Rule 1: Bits within a nibble must stay together.
      Rule 2: Nibbles may be swapped within a byte.
      Rule 3: Definition of mapping is for Rank #0 only. Rank #0 to Rank #1 mapping is to swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and swap bit 6 with 7. This does not apply in certain cases (for example, dual rank x4 VLP RDIMM with traditional DDP).
      In such cases, the mapping of rank 0 to rank 1 is 1:1 and does not use the swap as described in Rule 3. Therefore, the DDRC.DQMAP5.dis_dq_rank_swap register is provided to control Rule 3.
AR# 67330
Date Created 06/03/2016
Last Updated 06/07/2016
Status Active
Type General Article
Devices
  • Zynq UltraScale+ MPSoC