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AR# 67384

Vivado - [Place 30-678] Failed to do clock region partitioning


When running implementation, the following error from place_design is seen:

Phase 2 Global Placement
ERROR: [Place 30-678] Failed to do clock region partitioning: Clock routing needed to place clock source u_california/u_lax/u_ahbpmu/u_pmu/u_clm/u_clk_tport_mux0/u_bufgctrl at a new location so that clock net driven by this buffer can use a specific clock route track, but this operation failed as no BUFGCTRL site in clock region X2Y3 is available
Resolution: Try removing the area constraints set on the clocks (source and/or loads) that compete for resources in the same clock region(s). In case an area constraint on the clock loads is necessary, please either extend the area constraint to cover the clock source, or make sure that the clock source is constrained/placed in a clock region in the same row or column as one of the regions in the specified area constraint. Also try reducing the amount of clock resources in your design, by either combining some clock nets or by changing the placement of clock primitives to reduce the distance between the source and loads of each clock net involved in the area with higher clock routing utilization.

What is causing the contention?


There can be many reasons for the contention, but for this example, a specific clocking structure resulted in the contention.

This use case has two MMCMs driving five multiplexing BUFGCTRLs (MMCM -> BUFG -> BUFGCTRL).The image below shows that a BUFGCE (red) and driving MMCM are located in the center of the device.

The BUFGCTRL (pink) is then placed at the top of the device, and drives another BUFG (yellow). However, some of the loads end up towards the bottom of the device.

Having the clock routes go up and down the device like this causes the contention and failure.


Below is an image of the full structure:


This is not an expected use case for Vivado to place. While there are rules for the MMCM -> BUFG paths, there are no rules for the BUFG -> BUFGCTRL -> BUFG paths. There are two options to work around this issue:

  1. Use the CLOCK_REGION constraint to constrain the BUFGCTRL instances to the center of the device, which will alleviate the contention. With limited BUFGCTRL resources, different values for the CLOCK_REGION constraint might be needed.

  2. Use a pblock for the complete clock structure to ensure that these are placed in the center of the device.
AR# 67384
Date Created 06/14/2016
Last Updated 08/16/2016
Status Active
Type General Article
  • Vivado Design Suite