A design that uses the UltraScale FPGAs Transceivers Wizard to generate several GTYs has been successfully implemented in a VU9P UltraScale+ device.
I am now attempting to migrate this design to a VU13P UltraScale+ device.
Leaving the original IP generated for the old VU9P device, global synthesis is run with the new part VU13P.
However, when I open the synthesized design I do not see the expected I/O PACKAGE_PIN locations of the GTYs as defined by the UltraScale and UltraScale+ Packaging and Pinouts Guide (UG575).
For example, the VU9P has GTYs that use bank 123. When synthesizing with the VU13P part, it is expected that bank 127 should be used referencing (UG575). This does not happen, as bank 124 is used instead.
This can be confirmed by opening the synthesized design and viewing the I/O Ports tab. What is causing the discrepancy?
This issue is caused by the way in which the constraints are propagated to the new part.
The Transceivers Wizard PACKAGE_PIN constraints are based on the GTYE4_CHANNEL site used. There is a difference between the number of banks in a vertical SLR column in each device (5 for the VU9P and 4 for the VU13P), and this results in a misalignment.
This issue might be seen on similar migration paths. Specifically, if a design is based on a device with a five row tall SLR like the VU160/VU190/VU7P/VU9P and is migrated to a four row tall SLR device like the VU11P/VU13P, the quad number mismatch will occur.
It is recommended to re-generate the Transceivers Wizard IP for the new part. The re-generation will have the correct constraints generated for the specific target device.