UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 67412

Zynq UltraScale+ MPSoC: 2016.2 FSBL, Added DDR ECC Initialization feature

Description

In order to add ECC support to the DDR, the FSBL needs to handle the following:

  • Specific DDR Configuration
  • Initializing the DDR to a known value

Solution

In Vivado 2016.2, FSBL now supports DDR ECC Initialization.
AR# 67412
Date Created 06/17/2016
Last Updated 06/22/2016
Status Active
Type General Article
Devices
  • Zynq UltraScale+ MPSoC
Tools
  • Vivado Design Suite - 2016.2