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AR# 67439

Design Advisory Vivado 2016.1 and 2016.2: Incorrect LUT equation seen when ILA probe is placed on an LUT1 inverter that drives other LUT logic

Description

This Design Advisory describes an issue where an incorrect LUT equation is seen when ILA probe is placed on an LUT1 inverter that drives other LUT logic.

In this example design, ILA cores have been added for debug purposes. It can be seen that the LUT equation after opt_design does not match with the LUT equation before opt_design.

Below is the schematic and truth table of the LUT before opt_design and after opt_design.

 

In the before and after screen captures below, note that the LUT3's truth table equation is changing to accommodate an inverter push to the I1 pin of the LUT3, but the LUT1 inverter driving the I1 pin has not been removed from the after schematic as it should have been.

 

Before running opt_design:

 


 

 

After running opt_design:

 


Solution

This is due to an issue with inverter pushing during optimization incorrectly adding an additional inversion to the path.

The LUT equation of the load LUT is being changed but the inverter that was pushed is not removed from the path due to the presence of the probe, and so an extra inversion is being added to the path.

Symptoms:

This issue can lead to a design failing in hardware after ILA probes have been added to the design.

 

The following INFO message will be seen in the log regarding the inverter pushing.

INFO: [Opt 31-138] Pushed 2 inverter(s) to 38 load pin(s).

Resolution:

This issue has been fixed for Vivado 2016.3 In the meantime, several work-arounds are available for use in 2016.1 and 2016.2:

 

Option 1:

Set the following parameter:

set_param logicopt.enablePartialInvPushingInPresenceOfDTBoundaries 0

This parameter disables the faulty inverter pushing behavior. It is possible to add this parameter setting to the init.tcl file so that it is automatically set for all projects. 

See (UG894) page 18 for details on using init.tcl. This solution is recommended to ensure that all users and projects are protected from this inverter corruption.

 

Option 2:

Set a DONT_TOUCH property to TRUE on either of the LUT cells involved using the following XDC constraint:

set_property DONT_TOUCH TRUE [get_cells LUT_instance_name]

A Tcl script (find_lut1_md.tcl) is attached to this Answer record which detects LUT1 inverters that drive MARK_DEBUG nets. It reports the name of the LUT1 and applies a DONT_TOUCH property to it. 

The script can be used to prevent this problem if run prior to opt_design or to detect the problem if run after opt_design. The tcl.pre feature can be used to run this script automatically prior to opt_design.

 

Option 3:

Move the probe so that it is not on an LUT1 inverter output. This will also result in fewer logic levels as the probe interferes with inverter pushing.

Attachments

Associated Attachments

Name File Size File Type
find_lut1_md.tcl 354 Bytes TCL
AR# 67439
Date Created 06/23/2016
Last Updated 08/02/2016
Status Active
Type Design Advisory
Devices
  • FPGA Device Families
Tools
  • Vivado Design Suite - 2016.2
  • Vivado Design Suite - 2016.1