In systems using JESD204B Sub Class 1 interfaces to communicate sample data between data converters and Xilinx All Programmable Devices, it might be preferable to employ a simple method of synchronizing the interface in a repeatable manner.
(PG066) details the procedure for calculating the magnitude of End-To-End latency of JESD204B systems, while simultaneously ensuring that latency is robustly repeatable.
In some cases, the only requirement is for the delay to be robustly repeatable, and the absolute magnitude of the end to end latency is not required.
This Answer Record describes an approach that can be used in such systems.
Note: An understanding of the deterministic latency mechanism used by JESD204B Sub Class 1 is required.
Figure 1 below shows the normal operation of a Xilinx JESD204B Sub Class 1 Receiver core.
Figure 1: Normal Operation
High speed transceiver based links such as those used for the physical layer in JESD204B do not maintain the same data path latency through a reset or a power cycle. As a result, issues can arise in systems where the start of data arrival at the receive core is very close to the LMFC boundary. Such systems might be unable to manage the small variability in delay through the link that can occur between restarts.
Figure 2 shows the start of sample data arriving "Just before" and "Just after" the LMFC boundary, illustrating the effect a restart can have. It can be seen that a very small difference in data arrival time at the core can cause a change in the timing of the output data equal to 1 LMFC period.
Figure 2: Data arrives "Just before" vs "Just after" the LMFC boundary
To protect against this problem, a margin must be introduced around the LMFC boundary, which the start of data must avoid. Figure 3 shows this margin:
Figure 3: LMFC Margin
The LMFC is a periodic signal, so a target window (TW) is required within which to aim. Figure 4 shows this window. If data can start within this TW, link robustness is ensured.
Figure 4: Target Window
The TW can generally be set reliably at between 2 CORE_CLK cycles before and 2 CORE_CLK cycles after an LMFC boundary.
Note: This assumes that any variation in the output timing of the ADC is less than four octets. If the output variation is greater than four octets, the margin can be increased and the TW decreased accordingly.
The solution is to adjust the internal LMFC relative to the fixed data arrival such that arriving data falls within the target window shown in Figure 4 above (i.e. move the window).
This is achieved by starting the link, and using core registers to determine the amount of data which was buffered, then taking steps to adjust the LMFC boundary until acceptable values are attained. This process should only be required to be performed once during development. When the system has been adjusted to ensure the data arrival is within the target window, it should not require further adjustment.
The registers used during this process are:
BUFFER ADJUST: The JESD204B core contains a readable BUFFER ADJUST register for every JESD204B lane. This register indicates how much data was in the lane alignment buffer for each lane at the LMFC boundary when the output data was released.
Note: The value in the BUFFER ADJUST register may be different for each lane due to inter-lane skew on the link. The value of interest is the smallest value of all the lanes. This marks the starting point in time when all lanes had valid data. This is the point where the core was actually ready to release data. The value in this register is a count in octets and there are 4 octets per CORE CLK cycle.
SYSREF DELAY: Located in the SYSREF HANDLING register: This register delays the internal LMFC boundaries relative to the SYSREF by an integer number of CORE CLK cycles. Therefore programming a SYSREF DELAY of 0x1 will cause the LMFC to be delayed by 4-Octets.
Steps to follow:
Calculate the Multi Frame (MF) size.
The larger the value of MF, the greater the target window will be. It is recommended to pick a value for K that results in a MF of at least 32 octets.
Calculate the TW maximum value in octets based on the MF size.
Configure the system and start the link. At this point all delays can be unknown.
Once the link is running, read the JESD204B RX core BUFFER ADJUST register for every JESD204B lane in use.
Select the smallest value read from the BUFFER ADJUST register and call this value BUF_FILL.
If BUF_FILL falls between the Min and Max value (calculated in step 2), the data arrival is within the safe TW and no further action is required.
If however, the BUF_FILL does not fall between the Min and Max values then the following action should be taken.
1) Program the SYSREF DELAY register with a delay value calculated as follows:
2) Reset the JESD204B receive core and reinitialize the link. This step must be performed before the modified SYSREF_DELAY value will affect the LMFC.
3) Re-read the BUFFER ADJUST register for every lane to confirm the data arrival is now within the target window.
The calculated SYSREF DELAY value should be stored for future use when configuring this link.