I have a FIFO Generator core with the AXI Stream FIFO in the "Independent clocks Block RAM" configuration.
I am seeing strange behavior in hardware; the m_axis_tvalid signal goes high after the reset signal is de-asserted when there is no valid data written in to the FIFO.
This issue was not seen with the earlier version Vivado 2015.4. Is this expected behavior of the core?
This issue is seen due to changes made to the Safety circuit of the IP in Vivado 2016.1.
The Safety circuit is always enabled when using the AXI interface with the "Independent clocks Block RAM" Configuration.
One of the following work-arounds can be used:
This issue will be fixed in Vivado 2016.3.