We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 67459

2016.1/2016.2 FIFO Generator: AXI Stream FIFO: m_axis_tvalid goes high after de-asserting the reset when there is no valid data written to the FIFO


I have a FIFO Generator core with the AXI Stream FIFO in the "Independent clocks Block RAM" configuration.

I am seeing strange behavior in hardware; the m_axis_tvalid signal goes high after the reset signal is de-asserted when there is no valid data written in to the FIFO.

This issue was not seen with the earlier version Vivado 2015.4. Is this expected behavior of the core?


This issue is seen due to changes made to the Safety circuit of the IP in Vivado 2016.1.

The Safety circuit is always enabled when using the AXI interface with the "Independent clocks Block RAM" Configuration.

One of the following work-arounds can be used:

  1. Ensure that the reset assertion/deassertion is not too close to the read clock to ensure that you meet the setup/hold requirements.
  2. Perform dummy reads until the m_axis_tvalid signal goes low.

This issue will be fixed in Vivado 2016.3.

AR# 67459
Date Created 06/27/2016
Last Updated 07/01/2016
Status Active
Type General Article
  • FPGA Device Families
  • Vivado Design Suite - 2016.1
  • Vivado Design Suite - 2016.2
  • FIFO Generator