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AR# 67484

2016.2 Implementation - Debug probe on output of LUT1 inverter interferes with inversion pushing, leading to corrupted LUT logic


LUT logic can be corrupted by a debug probe being applied to the output of a LUT1 inverter. 

The inversion is incorrectly pushed forward into a LUT2 input but the LUT1 is not removed, resulting in an incorrect additional inversion on that path.


This issue will be fixed for Vivado 2016.3. Until then it can be worked around by either moving the probe off the inverter output, or by applying a dont_touch property to the LUT1 inverter.

AR# 67484
Date 07/05/2016
Status Active
Type General Article
  • FPGA Device Families
  • Vivado Design Suite - 2016.2
  • Vivado Design Suite - 2016.1
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