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AR# 6749

Virtex Configuration - The DONE pin does not go High, and the INIT pin does not go Low


General Description:

When I attempt to configure a Virtex device, the DONE pin does not go High, and INIT does not go Low. What is causing this?


There are several reasons that this situation may arise:

- The Virtex synchronization word is not being caught.

- A bit is being added or lost.

- An incorrect STARTUPCLK has been selected.

The Virtex synchronization word is: AA995566

The first two hexadecimal values of "AA" are represented in a binary byte as:

1010 1010

The Most Significant Bit of each byte must be on the D0 of the Virtex device (for SelectMAP). In this case, this means that the left-most 1 will be fed on to D0, the adjacent 0 will then be on D1, etc.

Be sure that you are presenting the data appropriately on the Virtex data pins.

More specific causes of the DONE pin not going High are documented in (Xilinx Answer 2149), (Xilinx Answer 8022), (Xilinx Answer 8240), and (Xilinx Answer 11004).

If a bit (or byte) is added or lost during configuration (perhaps because of clock glitching or noise), the rest of the bitstream will be misaligned. Each packet after the false edge will be one clock off, so the Virtex device cannot properly recognize them. Thus, no more data will be loaded, and no CRC will occur; this causes the INIT pin to stay High, and the DONE pin to stay Low.

An IBIS simulation may be warranted, depending upon the board configuration. CCLK is an LVTTL 12mA buffer, and it is wise to simulate the board traces if the data or CCLK line is longer than 2-3 inches.

The device is not fully active until it proceeds through the startup sequence, and the correct clock must be selected in order for the device to be clocked through this sequence. The three startup clock options are: CCLK, the JTAG clock (TCK), and a User clock (which is an input to the STARTUP block).

The default is CCLK. You can check the option by inspecting the BitGen option file (bitgen.ut file) or looking at the BitGen report (design.bgn) to examine the command line options. The syntax is:

-g StartupClk:CCLK or

-g StartupClk:JTAGClk or

-g StartupClk:UserClk

If the incorrect clock is chosen, DONE will not go high, and INIT will not go low.

AR# 6749
Date Created 08/21/2007
Last Updated 12/15/2012
Status Active
Type General Article