Designs using the 10G/25G Ethernet Subsystem with the transceiver in the example design can fail synthesis or encounter timing errors.
Designs featuring the10G/25G Ethernet Subsystem can fail OOC Synthesis when using BASE_R and one step timing mode, with the following errors:
These issues are fixed in Vivado 2016.3.
In Vivado 2016.2 you can install the patch attached to this Answer Record to resolve the issue.
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