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AR# 67563

Vivado 2016.2 - 10G/25G Ethernet Subsystem - Synthesis fails when one step mode is selected in BASE_R or if the transceiver in the example design is selected

Description

Designs using the 10G/25G Ethernet Subsystem with the transceiver in the example design can fail synthesis or encounter timing errors.

Designs featuring the10G/25G Ethernet Subsystem can fail OOC Synthesis when using BASE_R and one step timing mode, with the following errors:

[IP_Flow 19-167] Failed to deliver one or more file(s).
 [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'xxv_ethernet_2'. Failed to generate 'Verilog Simulation' outputs:
 [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'xxv_ethernet_2'. Failed to generate 'Verilog Simulation' outputs:
 [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2016.2/data/ip/xilinx/xxv_ethernet_v1_3/ttcl/mac_baser_core_top.ttcl': can't read "C_PTP_OPERATION_MODE": no such variable

Solution

These issues are fixed in Vivado 2016.3.

In Vivado 2016.2 you can install the patch attached to this Answer Record to resolve the issue.

Attachments

Associated Attachments

Name File Size File Type
AR67563_vivado_2016_2_rev1.zip 15 MB ZIP
AR# 67563
Date Created 07/20/2016
Last Updated 08/25/2016
Status Active
Type General Article
Tools
  • Vivado Design Suite