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AR# 67572

Virtex-7 FPGA VC707 Evaluation Kit - UG885 (v1.7) - Table 1-5 U1 Pin for Flash address is incorrect

Description

(UG885) VC707 Evaluation Board for the Virtex-7 FPGA User Guide (v1.7), includes the BPI flash memory connections to the FPGA in Table 1.5.

FLASH_A21 and FLASH_A22 nets are both assigned to the FPGA (U1) Pin, is this correct?


 

Solution

There is a typo in Table 1-5 of UG885 (v1.7).

FLASH_A21 should be assigned to pin BA40 of U1 FPGA, while FLASH_A22 should be assigned to pin BA39 of U1 FPGA.

This has been corrected in UG885 (v1.7.1).


 

AR# 67572
Date Created 07/22/2016
Last Updated 08/25/2016
Status Active
Type General Article
Boards & Kits
  • Virtex-7 FPGA VC707 Evaluation Kit