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AR# 67622

2016.2 - VHLS - C Simulation fails with the error @E Simulation failed: SIGSEGV


C simulation fails with the following error:

INFO: [SYN 201-201] Setting up clock 'default' with a period of 4ns.
INFO: [HLS 200-10] Setting target device to 'xcku040-fbva676-1-c'
make: `csim.exe' is up to date.
make: Warning: File `csim.mk' has modification time 27 s in the future
make: warning:  Clock skew detected.  Your build may be incomplete.
@E Simulation failed: SIGSEGV.
CRITICAL WARNING: [SIM 211-1] CSim failed with errors.
    while executing
"source /../../../B_ge114_provm_v2.0/development/backend/XCKU040-1FBVA676I/hls..."
    invoked from within
"hls::main /../../../B_ge114_provm_v2.0/development/backend/XCKU040-1FBVA676I/..."
    ("uplevel" body line 1)
    invoked from within
"uplevel 1 hls::main {*}$args"
    (procedure "hls_proc" line 5)
    invoked from within
"hls_proc $argv"
Finished C simulation.


This error can occur when classes or class member functions are set as the top-level for synthesis.

Classes and class member functions cannot be the top-level for synthesis. You must instantiate the class in a top-level function.

To synthesize a class member function, instantiate the class itself into a function. Do not simply instantiate the top-level class into the test bench.

AR# 67622
Date Created 08/01/2016
Last Updated 08/11/2016
Status Active
Type General Article
  • FPGA Device Families
  • Vivado Design Suite - 2016.2